Design Flow

• Generate P&R Views
• Generate Timing Views
• Generate RC Rules
• Generate Noise Rules
• Run Cell Analysis
• Run Early Correlation

• Design intent is captured in either Verilog or VHDL languages
• Test benches are written in the above std HDL's or verification-specific languages
• Performed by the customer

• Conversion of RTL to Gate Level Netlist
• Constraint-driven
• Targeted to a specific silicon process and library

At this stage of the design flow, Fastrack designers generate a gate level implementation of the design, targeted to a specific silicon foundry. Timing constraints, such as clock information, input arrival times, output required times, input driving cells, output loading, false paths, multi-cycle paths, etc. are defined in a detailed level. With these constraints in place and a library defined, the designer runs synthesis to convert the RTL description into a gate level netlist.

At this stage, hierarchical blocks are identified & what-if analysis is performed to compute estimated die size.

• Physical block partitioning
• Assignment of block sizes and pinouts
• Timing budgeting and block level constraint generation
• Memory and macro cell placement
• Power and clock distribution planning

Fastrack designers can easily integrate tradeoffs and constraints to map the logical design into the physical domain. Decisions made at this step are critical to successfully completing the chip through place and route, while meeting performance and area constraints.

• Driven by system level timing constraints
• Automated timing driven placement
• Clock tree synthesis
• Signal and power routing
• Signal integrity

Fastrack utilizes a timing-driven place and route methodology that incorporates timing constraints similar to those used during static timing analysis and synthesis. This methodology helps avoid costly iterations that are prevalent in non-timing driven methodologies.

• Lower level hierarchical blocks are connected at the top level
• Power & clock are routed
• Top level is routed
• All chip integration related issues are addressed

Top-level assembly is probably one of the most challenging steps in design implementation. Problems with time budgeting will be revealed here.

• Extraction of routing parasitics
• 2.5D and 3.D algorithms
• Back annotation to static timing analysis, gate level simulation and other front-end processes

This step occurs at several points during the place & route process, such that the highest level of accuracy is incorporated into the resulting interconnect delay calculation.

• Verifies that chip performance is met
• Setup, hold and I/O timing checks are performed
• Best and worst case analysis
• Pre and post layout

All timing paths in the design are exhaustively examined, under a given set of timing constraints.

• DRC, LVS and antenna checks
• Metal density, slotting and other special rules
• Final database preparation

Fastrack designers have experience in successfully delivering designs to all of the major commercial foundries, and are adept at incorporating special rules into the final release process

All timing paths in the design are exhaustively examined, under a given set of timing constraints for final signoff.

Cross talk noise, cross talk delay and signal electromigration checks are performed using a sign off quality signal integrity checking tool.

• Closely work with customers for optimal planning, task coordination, communication and documentation
• Full project life-cycle objective professional management
• Fair contract terms and conditions

Fastrack has a disciplined program office dedicated to communication, documentation, project execution excellence, and customer satisfaction. Project scope, customer inputs, Fastrack deliverables, design constraints, assumptions, schedule and quality are clearly defined and executed to, during the entire engagement.

• 'RTL to Gate' after synthesis to verify the RTL Mapping & optimization
• 'Gate to Gate' to verify the P&R timing optimizations, clock tree additions and scan reordering
• Supplements traditional approach of re-simulating the design

Fastrack can perform this advanced technique to verify that the design remains functionally identical throughout the design process.

• BIST
• JTAG
• Scan insertion
• ATPG

Design for test encompasses many aspects of the design flow including insertion of scannable flip-flops (scan insertion), adding BIST (Built-In Self Test) for both logic and memory elements, and adding JTAG (Joint Test Action Group) for I/O.

• Understand the physical aspects of the design
• Provide feedback on the quality of the netlist
• Automatic generation of layout constraints for rapid design closure